Rambus Inc. has revealed the technical specifications of its quad-speed chip interface, which taps some hard-won design modifications to double the bandwidth of the current Rambus interface without altering its clock frequency, EETimes.com reported on Friday.
Rambus engineers said they expect the quad interface, which can transfer data at 1.6 Gbits/second per pin, to be used first in communications or consumer applications, such as game machines, even as DRAM makers continue to crank up the speed of current Direct Rambus devices, which target PCs.
"We're not trying to replace PC memory" with the new Quad Rambus Signaling Level (QRSL) technology, said Kevin Donnelly, vice president and general manager at the Mountain View, California-based Rambus. "This would fit well with graphics, consumer and communications."
In the communications space, Donnelly said, Rambus is in discussions with a major networking company "whose name begins with a C."
EETimes.com quoted the official as saying that the networking company is exploring the interface for use in an OC-192 line card network processor with six chips on a board. The customer is interested in the interface to link the processors and has 600 I/O pins to work with, a constraint Donnelly said QRSL can easily meet.
Billy Garrett, a Rambus strategic marketing manager, said Rambus will introduce products later this year that are optimized for the communications market, based on the existing Rambus Signaling Level (RSL) technology. For QRSL, Garrett said, "all we announced was the signaling technology," not a product strategy.
The demands of the communications market "are different from those of the PC world. Products from Rambus will be introduced over the next couple of quarters aimed at communications, using RSL," Garrett said.
He also noted that QRSL technology could be used in SRAMs, which often fit the needs of network systems companies better than DRAMs.
Memory devices using the QRSL interface may be used in game consoles, where Rambus has enjoyed success in Nintendo 64 and, more recently, Sony's Playstation 2. Toshiba Corp., which makes Direct RDRAMs for Playstation 2, is the first company to announce it has licensed QRSL, saying it will use the interface for consumer and communications applications but offering no specifics.
"In game machines, we see memory systems that must get as much bandwidth as possible in a single chip," Donnelly said. "In a server that has a wide memory bus, people can make the argument that it's not as important."
Meanwhile, although it is not targeting PCs initially, Rambus' promise of 12.8 Gbytes on a 64-bit bus is likely to catch the attention of some PC OEMs. But for now there is one major handicap: It can only link four devices for every channel. The current Direct Rambus interface, by contrast, can string together up to 32 chips per channel.
"QRSL simplifies development from a signal integrity and physical interconnect point of view," Donnelly said. "It's not that we're limited to just four [devices per channel]. We've analyzed four per channel, and we've seen results at 16. But most customers in consumer applications are interested in one to four. Later we can develop connector modules, as we did with Direct Rambus."
QRSL-based devices won't hit the market until 256-Mbit or 512-Mbit densities are mainstream. For a game machine, a few chips will provide the needed densities, Bob Merritt, a senior analyst with Semico Research was quoted as saying by EETimes.com.
Merritt said Rambus managers told him that any chips based on the QRSL signaling technology must be soldered to the motherboard and not stored on the modules that the PC industry typically deploys, partly for inventory and memory-upgrade reasons.
If Intel Corp. and the PC industry cannot use the QRSL devices, it could prove difficult to bring down costs for QRSL-based memory uses in the communications space, Merritt said.
Also, a limit of four devices per channel will make QRSL practical only for low-density consumer products, such as Playstation 2. Even if that Sony platform creates a market for QRSL memories, the volumes won't be high enough to drive commodity pricing.
"Rambus' corporate capitalization is largely based on its success in the midrange PC market, and that depends on Intel," the Semico analyst said. "Without the PC market, the QRSL technology costs may be too high to be competitive in the communications space."
Nevertheless, Merritt said he believes a packet-based memory architecture such as Rambus is better-suited to communications apps, which require small amounts of fast memory, closely coupled to the processor.
Steve Cullen, a Boston-based memory analyst for the Cahners In-Stat research organization, said he also believes the basic packet approach pioneered by Rambus will prevail in the communications sector. "Handling packets of [Internet] data may be a problem that, at a high level, the Rambus approach may be able to fix," Cullen said.
Under development since 1997, QRSL technology is intended to overcome the bandwidth-killing phenomena, caused by greater device loads and such other factors as the increased use of low-cost packaging, that occur as frequencies get pushed ever higher.
"It's a question of how soon you're going to hit this wall," said Jared Zerbe, circuit design manager at Rambus. "For example, at 400 MHz the data I'm pushing through starts attenuating. There's a loss of signal due to the parasitics of the loads, and each of the devices has a capacitor and inductor, so the amplitude of the signal becomes smaller and smaller, and recovering data error-free becomes harder."
Using multilevel signaling, Rambus can take advantage of the boards, clock circuits, modules and packaging used for Direct Rambus. Essentially, the QRSL interface runs at the same speed as Direct Rambus but transfers 4 bits, instead of 2, at every clock edge.
Most chip interconnect technology detects binary information using two voltage levels. Direct Rambus, for example, has an 800-millivolt voltage swing between 1.8 and 1 V, with 1.4 V as a reference. QRSL, on the other hand, divides the voltage into four levels with the same voltage swing, each level representing 2 bits of information (00, 01, 11, 10).
Flash memory vendors were the first to break ground in this area, using multilevel voltages to store 2 bits in one memory cell, although Merritt noted that Intel's StrataFlash approach to storing 2 bits per flash cell differs greatly from the QRSL approach.
For the flash vendors, developing multibit technology has been difficult, largely because slicing the voltage into smaller pieces leaves less to work with. When Intel first introduced its StrataFlash technology several years ago, for example, it kept the operating voltage at 5 V, even though 3 V was becoming mainstream.
Zerbe acknowledged that splitting up voltages is not an exercise for the faint of heart. "By dividing the voltage, people might say we're crazy because it's difficult to get voltage margins in a normal system," Zerbe said.
To get around the problem, Rambus used integrating receivers to remove high-frequency noise on the signal or reference. There are two receivers for each pin: one that compares the input voltage to a reference voltage, and a second region that has two reference voltages, to determine whether the input voltage lies between them.
Since the single-reference voltage receiver is the same as that used in a Direct RDRAM, the dual-reference voltage receiver can be set to zero, so that a device with a QRSL interface and RDRAM interface can talk to each other. "It allows us to put in a mode to receive or transmit the same levels as a Direct part," Donnelly said.
Rambus kept the latency equal to that of Direct Rambus by using a folded pre-amplifier design, to reduce the number of sense-amp stages, as well as an optimized coding scheme. Short of reducing the CAS latency of a DRAM, there's little more that could be done to reduce latency using the new interface, Donnelly said.
"We worked very hard to make sure [the latency would be] the same as Direct [Rambus]," Donnelly said. "We added a few picoseconds here and there but didn't add any cycles, and that's the key metric."
Though Rambus has fabricated a test chip based on 0.35-micron technology, there are no real devices using the interface to show what it can do in an actual application. But Rambus said there is nothing stopping a licensee from using the interface today. A DRAM maker should not have to make significant changes to the core design, other than perhaps add more banks. Currently, Direct RDRAMs have up to 32 banks.
One larger issue will probably be testing, which is already a costly endeavor for DRAM vendors that make Rambus parts. "One of the biggest concerns is that they haven't tested a multilevel pad before," Donnelly said.
Rambus and some of its DRAM partners will soon announce a speed upgrade for Direct Rambus, a packet-based DRAM with speeds of 600 to 800 MHz. (Rambus clock speeds actually run at 400 MHz - half the advertised frequency - but use a double-data-rate scheme in which data is transferred at both the rising and falling edges of the clock.)
The speed increases would come from DRAM process shrinks, which scale down power consumption and die size while boosting transistor speed. According to Rambus officials, DRAM vendor Samsung claims it can increase Direct Rambus to 850 MHz at the 0.21-micron process node, 910 MHz at 0.19 micron and 1 GHz at 0.17 micron -- Albawaba.com
© 2000 Al Bawaba (www.albawaba.com)